Okay, welcome.
I'm Wade Krabinski.
Wade Krabinski, and you can start.
Okay. Good morning.
Oh, it's already a good afternoon.
I'm here to introduce all the larger selection
of FOSS Free Open Source software for IC design.
And mainly all we believe can support local European open access PDK in the shot.
This is what I'm presenting here.
It's a little bit compatible or related to previous talk where Team Nukap did
introduce all and then Felix introduced one of the circuit device level simulators.
This is a huge collaborative work.
If you feel I should include your name here, just let me know.
I'm consultant to IHP.
This is a research institute in Germany.
And they are very first in Europe to join Open Access of Free PDK Initiative.
René, Sergei, Christoph, Alexey, they are from IHP and they are personally involved
in the Open Access PDK development providing technical engineering support.
There are a couple of guys like Mario Pascal Marcos.
They are working on Verilog compiler.
There are teams working on the models, supporting Quax development.
I already mentioned Al and Davies from Nukap.
NGiSpy's team, by the way, they will present NGiSpy's tomorrow at Kaikad Devroom.
We have independent contributors, high level, well recognized professor,
Luca Benini, Boris Murman, also in the US, contributing to Open PDK.
Mad Vent is very strong promoter of this initiative and last but not least,
Tim Hansen from Google who was very first to push towards Open Access PDK.
So I will start with brief motivation.
Why Open PDK is so critical, not only here in Europe but at international level.
Also in a certain sense as a platform to teach, educate younger generation of designers,
both analog, RF, digital.
I have referenced not really Open PDK but quite important in Shatif in India, the FOSI.
A couple of examples of status of Open PDK around the globe.
Then I will introduce all what IHP did to enable, open enable access to IC manufacturing
and setting up complete tool chain of software packages to support design at different level.
So static layout, verification, validation, because the process is more towards analog RF application.
This is the level which we want to focus.
A couple of other points, I hope it could be interactive, really understanding where we are
and what are next steps, what are important task to undertake to not really consolidate
by bring all enthusiasts, volunteers, hobbyists, designers around Open PDK initiative,
making a roadmap and then understanding status, think about all the challenges and opportunities
which this initiative bring to the design, IC design community.
Motivation, I guess you are also following all about European chip-act.
This is discussion of over the last two, three years it's coming into power, into the execution.
But following even public hearings here in Brussels at European Parliament, such case as an attempt to draw more attention,
bring younger generation of designers to our domain, wasn't address.
And at one of the public hearings of chip-axe here at EU Parliament, here in Brussels,
only Jodebock, the VP of IMAIC address this point, that we can have new fobs, new production line,
but we need new designers to bring new chips, new product to these fobs.
Fabs are not running by themselves, they need the design.
Exactly a year ago, less than a month, a year ago he repeat this questions again pointing to the main topic,
how to build talent and skills to support IC design, not only in Europe,
IC international conference run in US, how to bring this talent and skills, how to enable access.
And we believe that OpenPDK could be also teaching education platform to draw more attention and bring talents to our IC design domain.
I'm showing this slide, it's not really OpenPDK, but it's...
This is initiative, there was a group of volunteers in Mumbai at Technical University of Mumbai,
and they set up really nice teaching educational environment, mainly using NG-SPICE and CHICA to introduce even teenagers to micro electronics,
starting with very simple examples like Flip-flop, small generator blinking LEDs,
and they were guiding them through this very simple design process with simulations,
helping design even PCBs assembled boards.
This runs for a couple of years, each year they have more and more contributors,
they were talking about something like couple of thousands volunteers supported this initiative.
It's not about design itself, but they create huge packages, libraries of tutorials,
they call them spoken tutorials, mainly in English as you can guess in India,
but they start to translate into other languages, they were talking about French, Spanish,
opening this facility for teaching in education also in local native languages.
It's teaching education platform, but they recognize importance of free open source tools,
and we have these two cases of NG-SPICE and CHICA.
OpenPDK was triggered by Tim Ansel in the US, it's running for a couple of years,
they partner with Skywater, they open the FAP, they release PDKs as open source,
FAPLES was quite instrumental, helping creating all the infrastructure,
they built certain tool sets to help teenagers, students, young researchers,
I see designers to complete design down to tape out and manufacturing.
There is a list of links about available resources.
Skywater as I mentioned was very first, Global Foundry joined a little bit later,
open two more processes, all a little bit kind of legacy, 180, 30,
I think Global Foundry going to 110 if I'm not mistaken.
So it's really a unique place where you can design, chip both analog RF, digital,
submit, tape out, manufacture, get even test board and complete all the design flow.
In Europe, as I mentioned, IHP, it's a research R&D institute in Frankfurt on other,
they recognize the importance of open PDK, and they, it's like middle of last year,
the organ released, they PDK for 130 bicemos process, and it's high end process,
the bipolar part here, BJTs are working at level of half a terahertz on silicon,
so 500 gigahertz on silicon, it's unique process, they open infrastructure,
they support multi-project quaffers on different level, academic development,
early access for commercial partners, start-up, SMC, SMEs, up to the multi-project,
complete chip integration.
Opening PDK is one task, what is also critical to understand what is really available in open source domain to support design,
and positive sense kind of consolidate all in this domain in particle from the developer point of view,
bringing all the tools working together, having equivalent to commercial tools like cadence or synopsis.
The workshop they organized last June was two days, even which brought tools developer, designers,
and all who are supporting this initiative, maybe from the back it's difficult to read the links,
my presentation is uploaded, you can get all updates or references on PDF which I uploaded.
So this is what I already mentioned, they are very first in Europe that there is no other Wafers Fab
R&D institution opening the PDK and helping to access multi-wafers projects to complete design and manufacturing,
because it's by CMOS process they are trying to target analog RF applications,
and of course opening this environment, a lot of questions how to make all the flow reliable, support.
In Germany they are quite lucky, German Ministry of Education recognize importance of this initiative and provide financial support,
so this from the basic entry up to multi-project wafers and fund services.
Bottom line is always money, so this is initial step, we have ongoing this discussion here in Brazil with European Union
to motivate them to support this initiative at European level as well.
This is the status, we have Sergei Heinebeck, he is PDK manager supporting this initiative at IHP,
all it's online on the IHP GitHub repository with project information, information about technology itself, devices,
cells, all the layout information, what is also unique, they are not opening PDK and SPICE library,
but you can also access all measurements data for semiconductor devices and passive components.
This is also important for others who are working on parameter extraction, model validation,
they have physical data to run all the checks.
There was a decision to use K-Layout as main tool for GDS generations.
We are extending this and the team which Sergei leads works on all the enhancement,
so you have to really follow up the GitHub repository to get all updates and new information.
There is still open discussion which tools we should put in the complete flow.
I mentioned K-Layout for GDS tool, X-Hemp for symbolic entry, schematic entry.
As the BISEMOS process targets RF application, modeling capacitive components, transmission lines,
parallel inductors, integrated antenna, we can benefit using other open source tools like open EMS
for electromagnetic simulation and device validation for RF applications.
Digital flow, here it's a little bit abstract view, I'm not a digital designer,
but all what is available here is well established for digital design, like complete open line,
open road flow where designers they can start with high level abstract definition, RTL,
behavioral, VHDL, Veriloc, go through this path, generate layout and submit new chip for production.
Later on I have a couple of digital examples which are already manufactured, tested and we have working silicon.
Again, all is uploaded so you want to capture slight but everything is online.
This is commonly used flow, open line or open road, but in France we have alternative tool chain choreolies
maintaining in France at Sorbonne University, Lipstick's department.
Unfortunately they were late to provide a slight covering day tools and tool chain they developed for digital design.
Again, references are in the slides so you can upload or check the slides and I guess it could be difficult to read from the back.
This is what we want to have also for IHP process, open PDK, complete analog IC design flow.
This is example from Stanford University where Professor Rihanna she set up all the tool chain for analog design and targeting sky water or global foundry PDK.
So they have schematic entry, circuit level simulator, layout tool and all the post processing verification, validation tools, DRC, LVS and again layout editor for final check before submitting tool chip for manufacturing.
Is silicon? They were supporting this and they provide standard pad frames where you can put your analog digital design.
Caravan in fact is the pad frame for digital circuits.
This is caravan for digital design.
They have also caravan pad frame for analog design where this part is set of instrumentation like signal generator, scope,
to measure your circuit without needs for external hardware to make final test after fabrication.
In Europe there is a group at University of Linz, Professor Prettell and his team.
They are providing seminal installer mainly as dockers where you can access these tools and set up your analog design flow.
Again, Linz at the very bottom.
This is a vision of IHP where they want to have complete analog RF open source design flow.
This is what Sergei prepared.
We are targeting Quax, it's open source simulator where it has reasonable and well established schematic entry editor.
This is a new Quax S and S stands for spies.
Quax can drive spies compatible tools, NG spies or ZYS.
Then, yes, so Quax is the front end, schematic entry in the background.
We have NG spies.
Then for layout, we are working directly, IHP works directly with K layout developers to make sure that all verification tools and options are available in K layout.
Including DRC, LBS, other verification tools.
I've mentioned about Open EMS, Electromagnetic Simulator.
This is a quite important extension to K layout where if you are RF designer, probably you have some RF components,
transmission lines, interconnect, spiral inductors, embedded antenna, and not all models are available in PDK.
So EMS helps to simulate these models.
As a result, you are getting set of S parameters which you can plug into your simulator and continue RF high-frequency design.
Parasitic extraction, it's critical.
You have to really understand how your design will operate at not only in gender speaking, how analog design will operate when it's prepared for manufacturing,
including all parasitic effects.
Of course, it's critical for RF too, but this is still on the discussion.
And then you do post-layout simulation, prepare the flies, and submit for tape out using IHP multi-project wafers.
There is a lot of discussion if this flow could be part of Euro practice.
Euro practice is the shell organization which provides tools and access to different technology,
so that the alternative path would be complete open source design tools till GDS tape out,
and they would help assembling multi-project wafers submitting to funders.
Just to introduce even teenagers or students at bachelor level to IC design layouts,
there is a couple of really nice tools.
This is Maud Van Silvitz where you can place their predefined layout of simple components starting with resistor or transistor.
There is CMOS inverter.
You are looking at layout not only to the representation, but this black line guide you for the cross section.
So you can see the topology of your circuits.
And from the layout, they can also generate very basic SPICE input file.
And in this case, we have also the SPICE input for inverter.
There is a bug.
If you spot the bug, let me know.
So this small challenge maybe for students.
Okay, we go further.
These two tools are part of design flows which are well established in the U.S.
I already gave you an example of Stanford using X-HEM for schematic entry,
and X-HEM was already set up for SkyWater Global Foundry,
and they did some work also for IHP by CMOS PDK as well.
For layout and all the tools,
verification tools, layout versus schematic,
DRC post-layout extraction, magic, it's still a core tool.
It's legacy tool, but it's maintained and well accepted by open source design community.
In IHP, they decide to go for K-layout as main layout tools.
And I mentioned about work in progress,
expanding and enhancing this tool to make this fully compatible with the design flow.
For schematic entry, we are still working with Quax Team,
which has a really nice schematic editor and well established interface for spies or ng-spies,
or generic speaking, spies-free simulation level,
and this library available, spies library available in IHP PDK.
There are some other teams in open source domain like this revolution EDA,
and they are also working on schematic editors.
They want to also add layout editor and set of the verification validation tools.
And again, if you want to learn more about other tools,
there are even videos introducing the tools which are available for design.
Yes, maybe a few words about EMS.
It's 3D electromagnetic simulator,
and they start with targeting mainly high-frequency antenna design,
and this tool can be also used for modeling simulations of IC components,
mainly passive transmission lines of spiral inductors.
And this tool, the IHP team who works with K-Lout and Open EMS
to integrate and make this smooth flow from the layout to the generation of 3D models
for numerical simulation to support RF device modeling.
As I mentioned, the eventual output of the models are as parameters,
which you can simply fetch and add to your transistor level simulation
to validate your analog RF circuits.
Yes, this is a snapshot of all different antennas which EMS can model and simulate
and generate a resulting as parameters.
Unfortunately, I was not able to bring a case of integrated elements from ICs,
transmission lines of spiral inductors, integrated antenna,
but this work is in progress, and again, the main Open EMS website is referenced below.
The talk before was also discussing all important enhancement to standard SPICE-free simulator.
GNU-CAP is an interesting alternative, and they are working on their model compiler.
As we are targeting NG SPICE as main transistor level simulation tool,
we have OpenVaf, which is a new, true, very low-A compiler,
not as it was before, where we had other tools which were generating model code,
C++ code, which had to be compiled and linked with the model.
Very low-A generator, the dynamic library, there is an extension to NG SPICE,
which accepts new models as dynamic libraries and allows you to simulate with non-standard models
which are not available in standard SPICE-free or NG SPICE.
This compiler takes care about all important elements of the model,
so it includes the currents, charges, the capacitances, and newest extension,
and enhancement is also supporting noise analysis for semiconductor device models.
This is fully integrated with the complete PDK flow, which we have...
We have references, and there is a pointer to today's presentation by Arlen, Felix,
and this eventually could merge with even better solution to bring new SPICE models
to GNU-CAP or NG SPICE in the future.
This is the case where we are illustrating implementation of new model into Quax.
The left-hand side is a snapshot of Quax schematic entry,
where you define your small sub-circuit.
It's a dummy example, just a single transistor.
Above you see all the tiny fields where you reference to PDK libraries,
because the model for transistor is not standard.
You have to also give a pointer to dynamic library,
which refers to MOSFET model.
In this case, it's PSP model, advanced MOSFET model for transistor level simulation.
With one click, you are getting results.
Single transistor, simple output characteristic of MOSFET device,
which is defined in the open PDK in the SPICE library of IHP Open PDK.
There is a lot of resources, main pointer for Quax as is here at the bottom of the page,
as references for all slides I'm presenting.
Tomorrow, there is quite interesting dev room.
They will discuss KiCut PCB design tools,
and part of the KiCut is also nice schematic entry.
Behind schematic, there is fully integrated NG SPICE to support circuit verification
before completing PCB design.
You can find pointer information about KiCut,
DeFrom, and Holger presentation, who will talk about NG SPICE
and complete integration in the KiCut design flow.
Almost immediately after opening IHP PDK, it's drawn a lot of attention,
and this is something I would not expect, but Professor Mourmann,
he is now at the University of Hawaii,
and here at close look at IHP PDK and prepare a series of classes
to teach his student, giving a real example.
Again, he set up in this case, it's one of the classes,
simple case of modeling or simulating MOSFET device,
with simple schematic example, and all the settings of control cards
to run SPICE simulation.
And this is a part of the teaching classes.
So this is also what we would like to see, the open PDKs as the teaching education platform.
Not only somewhere in the middle of nowhere in Hawaii, but in particular here in Europe.
Now, a couple of examples.
So all what we are presenting, it's last half a year,
but it immediately draws a lot of attention with some pre-announcements.
And here it's one of the real silicon which was submitted for tape out.
Team at ETH in Zurich, Technical University in Zurich,
they design a digital chip.
It's the RISC 64-bit RISC processor implementation.
And to complete design, they were using OpenRoute.
The very first implementation was already presented at Free Silicon Conference last summer.
If you would have a chance, I would strongly recommend to also join and eventually contribute to upcoming Free Silicon Conference,
which will be organized later this year at Sorbonne University in Paris.
We have Thomas, he's very active at Free Silicon.
He can give you updates about organization status of the conference.
So this, I'm not the digital design, but you can learn a little bit more about status of this tape out on the website.
And the silicon should be coming very, very soon.
So you can capture and deliver a similar presentation in China.
All of Rome are with mobile phones making screenshots.
Okay, this is internal IHP design, which was also completed using Open Source PDK
and the tools which we are trying to integrate.
And it's not only the layout or tape out.
There is a small photo of real Sekit, which is working, was measured and qualified.
Okay, the links, you probably have to click to get all updates on this project.
This is not directly implementation, Sekit implementation of design using IHP.
Professor Prettl and his team at the University of Linz in Austria, they make a couple of digital designs.
And they start working all these exercises with sky water.
But now they are in progress of like transferring the design and preparing new tape out using IHP by CMOS process.
And they should be ready soon with a tape out.
And all these exercises help us to improve the flow.
In particle analog part, we still need a lot of integration between different tools in this flow.
There is other paper by Professor Prettl and his team.
So it's open access paper.
So you can learn more about all the digital flow they are using to create or prepare the chip for tape out.
So again, X-hem for schematic, magic for layout.
There was some presentation today, earlier today about Yossi system.
All what we can have in open line, open route going down to all the files you need to complete layout and prepare tape out.
So there is a lot of documentation in a certain sense guiding you for the process, design process and helping you also setting up the tools on your side.
So now we are coming to the point that we have really a lot of available.
Again, FOSSI, ECME initiative, it's not open PDK, but they created platform to teach and to educate teenagers, beginners, students and maybe young injures to expose them to integrated circuit design.
Maybe on PCB level, but this is important point.
Other groups and organization like IEEE in Particle Solid State Circuit Society, they financially support small group students enabling access to IEEE.
Please, US organization enabling access initially to sky water and global fund that it PDKs.
And they are running hackathons and competitions for I think for second class tape out.
I was surprised that most of the design were coming from Pakistan.
So this draws attention truly internationally.
Of course, it's a little bit easier in US because they have huge sponsors as Google.
If FABLIS, they help them to manage designs creating all this reference, pad frames or analog design, pad frames or analog and digital circuits, which then manufacture always sky water or global fund.
There is initial work done also in Japan.
They call this minimal FABL and they are opening quite legacy process, but they are recognizing the critical importance of this again for teaching education.
And Europe, we are always behind and we have only one R&D wafer FAB, which opened the process as open PDK for circuit design.
Risk five, this group is huge.
I think this could be a reference for our activities.
They did excellent job bringing CPU to public to open source and there are plenty of tools supporting this digital design.
In case of our IHP open PDK, the target is analog RF, but of course we can also have digital chip and there were a couple of examples already.
So what we want to have cooperation, I mean this is the key point.
We want to help others to access PDK and removing this kind of legal barrier because it's open PDK.
You do not need to go through legal procedure, sign NDAs or have quite restrictive in many cases ED licenses.
We need more contribution to showcase the advantages of open PDK.
Within the last half a year there is a huge response and we have a couple of final complete integration, but it's coming from academia.
I hope this is our plan.
We want to show that this initiative has a huge commercial impact, mainly targeting smaller team, spin-off, start-up or SMEs.
All above, open PDK, NDAs, low level of free EDA tools can help them complete design and bring a piece of silicon to the market.
I think I touched the wrong connector.
So this is the list of challenges.
Yes?
The recording is stopped.
Ah, I'm run.
Okay, okay.
So let, I let you read and we create the base.
It's initial step and there are a lot of tasks to complete to make this smooth flow from schematic entry, layouts, verification tools up to tape out and final product.
We probably should take this offline and continue discussion.
If there is any input critical, constructive, I would be more than happy to collect all the information.
Closing.
Yes, without IHP, all what I'm presenting would be impossible.
Seger represent IHP.
If you have any technical question, I would recommend to talk to Sergey.
This was also recognized in Germany.
So there is financial support because the bottom line is money.
Software developer designers, they need a couple of euros to continue their activities and we appreciate all the financial support at the moment from the German.
They have this research my electronics in Germany and federal means of higher education and research.
They put a lot of money.
Now it's question will we manage to bring this to a European level and thinking about something European level research project to continue this.
Activities and financial support all in open source domain to develop design.
Of course, in certain sense, manufacturing.
So with this, I will close my presentation.
There are a couple of other events where we will be discussing presenting this.
You can read and again.
We have Thomas.
He's coordinating free Silicon Conference.
You can talk to Thomas.
This will be a central event where we'll discuss open PDK, complete design flow, analog, RF digital, accessing open PDK.
Open by IHP.
Hope that other European funders will join this and in shot event we will have broader selection.
Okay, by this, I will close.
I guess I over it.
If you have any question, I'm staying.
There is Thomas and Sergey.
We are ready to open your answer.
Any question?