Okay, LibreSock project is creating free and open source ship design for a family of system
on ship products for powering routers, cell phones, laptops, your laptop maybe in the
future.
So it uses the power extension set, augmented with 3D upcodes, accelerating 3D graphics
and also video acceleration upcodes and audio decoders and coders.
So we needed for avoiding right proprietary binary blobs and drivers and no reverse engineering
needed for supporting our hardware and well it is hard to do so we do it by grants and
donations, we use a pool of community experts on newsnet, IRC, academia and also commercial
partners which will produce our ship as you see later.
So it is architecture is a traditional fetch decode issue and execute pipeline but to increase
performance you use parallel decoders to decode instructions in advance, a vectored issue
so one instruction can generate many results at one time utilizing the functions units
of the ship with the parallel execution units and well managing all things scoreboard dependency
tracking design.
Well, we started from zero from the power is instruction set specification as published
by the open power foundation which is a open standard and you can submit the extensions
to it and that's one of the reasons we chose the power architecture.
So the power has this big manual with all the assembly instructions and all these formats
and we take these formats, these tables and auto-generate by Python and Python decoder
from these specifications and the specification of the power architecture also has a sealed
code and with this sealed code which is for humans but we use it for auto-translation
to a simulator, Python simulator and we start from the beginning just simulating instructions
in software then you use the simulator to test against this one, the last one and the
harder simulator will verify against the software simulator and finally FPGA and even an ASIC.
Let's jump here so this is like an imagine you have an add instruction coming in and
the LU has to process it but before processing it, it has to receive operands like add what
A and B but A and B can be the result of a previous instruction which is still being
processed so it has to wait, wait where, in here, in here and here and when it has to
have a read transaction, read the transaction then it will fill the buffers then the add
instructions can proceed and it will generate a result and condition codes but maybe you
cannot write them right now because you'll overwrite another instruction so we wait here
and here also and this has to be managed so one of my tasks is to simulate this to see
if it works well and do what? Formal verification which is so, so good, so, so interesting.
With normal simulation you just throw random inputs maybe and some test cases but how do
you know that you didn't hit a corner case? Well, the formal verification is like it's
try everything at once. Actually, it starts from a bad result that you don't want to have
and it shows you the input which reaches that bad result. Yes, so that's the bit of
the thing. We get a simple core, first we do not do these function units all in parallel
it just was one to test all of this is working put it here and then we read an instruction
which decode instruction and then run the instruction terribly slowly but we validate
the function units and the decoder. Next step which we do, we did already is we vectorize
it so we put a read 64 because there are 32 instructions you add vector prefix to them
and this vector prefix will tell you to read a predicate so from the vector you say no
I don't want all of them I want the even ones or the odd ones or the ones with pass
it a test like if then else but vectorized and then you run the vector loop so when instruction
again can generate many may take the place of many many instructions and well now we
go to the next steps we have this working now we have to do it in parallel we want to
have performance it is working now performance so to be a performant you need to while you
execute in one instruction you are decoding the next one you are fetching the next next
one and if there is a jump instruction by chance and it doesn't match what you are fetching
you have to reset the pipeline yes test well where you are right now we have a development
environment that any of you can download and test in your computer you can do it is running
in a shoot and then you can do make test to run the tests and if you have an FPGA board
you can compile the bit stream and put into a supported board and we even did a ASIC
with it well for the ASIC we need the PBK which is a process development kit that the factories
don't give it to you freely so that part is done by a third party we don't touch property
stuff but while it was done yes and we hope in the future to have a free PDK with it so
the FPGA is booted we have a bare metal like Arduino like FPGA team running Zephyr OS was
ported with network so networking was proved and the Linux with a serial console yes we
have the test silicon with that little a simple core and it is being carefully tested because
you have few chips produced one not to burn them so they are tested in a lab yes and the
parties underway with the new instructions vector instructions already and the new instructions
been submitted to the open power foundation for standardization and we are porting algorithms
cryptographic algorithms and multimedia etc. so what you aim we aim to port and boot a
Linux distro in the future eventually we want to have a full-term change GCC with vectorization
they find these tensions to include the texture upcodes for 3d acceleration so you notice there
will not be a GPU the instructions the CPU will be the GPU and well we need the hardware
and software developers and testers and also well documentation optional no okay so who
will build the chips well you just have research research money right well who produce thousands
of chips for the market well we are partnered with red semiconductor which is have the mission
of producing these chips producing a powerful and power efficient chip with our car so if
you see some of them some of us some of them with this logo on the shirts you can talk
to them you're here hello David hello people so that's it thank you very much thank you
very much for the presentation there's a few minutes left for questions so in the back
of the room I see someone waving just a moment thanks for your presentation you said that
you had some test chips going on what's the status of the bring-up like how far did you
get in the bring-up process okay we know the clock is working it has an well the azik
it's not only for Libresock but for the academic institution to test their design so they are
testing this the clock generation and well we know the clock generation works just that
so maybe anyone else with a question okay thank you for your attention.